1. Field of the Invention
This invention relates to a wiring structure of semiconductor device and particularly to a wiring structure suitable for VLSI and ULSI.
2. Description of the Related Art
The speeding-up of silicon (Si) semiconductor is performed by reducing the device size to increase the integration density of transistors formed on the single-crystal Si substrate based on the Moore's Law. At present, the production of 0.13 μm rule device has started. In 2005, it is planned to use ultra fine wiring with a width of less than 0.10 μm. A reduction in wiring width and wiring interval causes an increase in electrical resistance of wiring and in inter-wiring capacity and, therefore, the wiring signal propagation speed decreases according as the ultra fine process makes progress. It is recognized especially after the 0.13 μm rule that the problem of wiring delay adversely affects the operation speed of device. In the future development of Si semiconductor, the conversion of wiring material to new one is indispensable for increasing the wiring signal propagation speed since it is difficult to increase it by using the conventional ultra fine process.
The wiring delay can be reduced by using a wiring material with a resistivity lower than Al that is conventionally used as wiring material. In 1997, IBM Corp., USA developed copper (Cu) wiring. The resistivity of bulk Cu is 1.7 μΩ·cm while the resistivity of bulk Al is 2.7 μΩ·cm.
However, in making Cu wiring, since the vapor pressure of Cu etching product is low and therefore the semiconductor has to be heated to a high temperature, the process of Al wiring cannot be used that, as shown in FIG. 1A, Al thin film 2 is formed on the entire semiconductor substrate 1 and then a wiring region is covered with resist 3 and then the unnecessary Al uncovered is removed by etching. Therefore, another process of making Cu wiring is proposed that, as shown in FIG. 1B, a trench or viahole 11 with wiring width is formed in semiconductor 10 before forming Cu film 5 and then Cu atom is embedded therein and then unnecessary Cu part 6 is removed by polishing such as CMP (chemical mechanical polishing) (this process is called Damascene process). Further, since, in Cu wiring, it is necessary to prevent the diffusion of Cu atom to the Si semiconductor, a barrier layer 4 needs to be formed between the Si semiconductor and Cu (See e.g., Miki Moriyama et al., “Future Fabrication Techniques for Cu Wires used in Si ULSI Devices”, Materia Japan, Vol.39, No.11, pp.901–908 (2000), and Kazuhide Abe et al., “High Reliable Cu Damascene Interconnects with Cu/Ti/TiN/Ti Layered Structure”, Oki-Denki-Kenkyu-Kaihatsu, No.184, Vol.67, No.3, pp.65–68, (October, 2000)). Also, since Cu needs to be completely embedded into the trench or viahole, the thickness of Cu film must be reduced according as the wiring width decreases.
However, in forming the barrier layer by Damascene process, it is difficult to uniformly form the barrier layer in the trench or viahole. Furthermore, the barrier layer needs to have a thickness greater than 10 nm at thinnest portion in order to function as barrier layer for preventing the diffusion. As a result, the barrier layer must be thick to some extent and the resistivity increases due to the thickness. Still furthermore, the existence of barrier layer interferes with the reduction of wiring interval. Thus, a technique for forming Cu wiring without using the barrier layer has been researched.
On the other hand, from the viewpoint of the resistivity of Cu as wiring material, when the wiring width is reduced to 0.10 μm, that width becomes equal to mean free path of electron and, therefore, there is concern that the resistivity if Cu wiring material increases. This is because an increase in resistivity caused by electron scattering becomes significant according as the film thickness and average grain diameter decrease. Therefore, it is necessary to increase the average grain diameter in order to lower the resistivity of Cu wiring.
Furthermore, in case of Cu wiring, different from the case of Al wiring, there is concern that some crystal grains are preferentially grown when being kept at room temperature after the film formation to produce a nonuniform grain distribution and the reliability lowers due to dispersion of resistivity caused by the nonuniform grain distribution. Although the growth of large crystal grains contributes to a reduction in resistivity from the viewpoint of electrical resistance, it is necessary to control the microscopic structure of Cu wiring in consideration of both increasing and equalization of grain diameter in order to produce a nano-scale Cu wiring with low resistivity and high reliability.
The inventors have found that the growth of crystal grain depends on intrinsic strain (energy assist given to Cu film by the substrate) to be generated at the interface of Si substrate and Cu film. The invention is invented in researching the lowering of resistivity caused by increasing of crystal grain diameter, based on the growth process of Cu crystal grain in consideration of materials interposed between Si substrate and Cu film.